1. Field of the Invention
The present invention relates to a plasma addressed display system having a flat panel structure where a display cell and a plasma cell are mutually superposed, and more particularly to technology for realizing an enhanced resolution of pixels formed in such a plasma addressed display system.
2. Description of the Related Art
FIG. 7 shows the structure of an exemplary plasma addressed display system disclosed in Japanese Patent Laid-open No. Hei 4 (1992)-265931. As shown in this diagram, the plasma addressed display system has a flat panel structure consisting of a electro-optical display cell 1, a plasma cell 2 and a common intermediate sheet 3 interposed therebetween. The intermediate sheet 3 is composed of extremely thin sheet glass or the like and is termed a micro sheet. The plasma cell 2 is composed of a lower glass substrate 4 joined to the intermediate sheet 3, and an ionizable gas is enclosed in the gap therebetween. Striped discharge electrodes A and K are formed on the inner surface of the lower glass substrate 4. The discharge electrodes function alternately as anodes A and cathodes K. Since the discharge electrodes are formable by printing and baking on the flat glass substrate 4 by a screen printing process or the like, there are achieved superior productivity and working efficiency. Barrier ribs 7 are formed along each anode A of the discharge electrodes immediately above the anode and and which divides the gap where an ionizable gas is enclosed, thereby forming discharge channels 5. The barrier ribs 7 also are formed by printing and baking by a screen printing process, and the top of the rib is kept in contact with one surface of the intermediate sheet 3. A plasma discharge is generated between each of the anodes A on both sides and the intermediate cathodes K within the discharge channels 5 defined by pairs of the barrier ribs 7. The intermediate sheet 3 and the lower glass substrate 4 are joined to each other with glass frit or the like.
The electro-optical display cell 1 is composed of a transparent upper glass substrate 8. This glass substrate 8 is bonded to the other surface of the intermediate sheet 3 spaced by a predetermined gap with a sealing material or the like, and a liquid crystal 9 is enclosed as an electro-optical substance in this gap. Signal electrodes 10 are formed on the inner surface of the upper glass substrate 8. Matrix pixels are formed at intersections of the signal electrodes 10 and the discharge channels 5. A color filter 13 is also provided on the inner surface of the glass substrate 8, and three primary colors R, G, B for example are allocated to the pixels. The flat panel structure of such constitution is a light transmission type where, for example, the plasma cell 2 is positioned on the incident side while the display cell 1 is positioned on the outgoing side. A back light 12 is attached to the plasma cell 2 side of the display.
In the plasma addressed display system of the type mentioned, the row discharge channels 5, where plasma discharges are generated, are scanned line sequentially, and display driving is executed in synchronism with such scanning by applying an image signal to the column signal electrodes 10 on the display cell 1 side of the display. Upon generation of a plasma discharge in the discharge channel 5, the inside of the channel is brought substantially uniformly to an anode potential, and rows of pixels are thus selected. That is, the discharge channel functions as a sampling switch. When the image signal is applied to the pixels in an on-state of the plasma sampling switch, sampling is performed to thereby control turn-on or turn-off of the pixels. Even after the plasma sampling switch is turned to its off-state, the image signal is held as it is in the pixel. More specifically, in response to the image signal, the display cell 1 modulates the incident light received from the back light 12 into outgoing light and then displays the image.
FIG. 8 is a typical diagram illustrating two pixels extracted from a display unit. In this diagram, only two signal electrodes 101 and 102, one cathode K1 and one anode A1 are shown to facilitate understanding of the invention. Each pixel 11 has a layered structure consisting of signal electrodes 101, 102, a liquid crystal 9, an intermediate sheet 3 and a discharge channel. During a plasma discharge, the discharge channel is substantially hold at the anode potential. When an image signal is applied to the signal electrodes 101 and 102 in this state, an electric charge is injected into the liquid crystal 9 and the intermediate sheet 3. Upon termination of the plasma discharge, the discharge channel is returned to its insulated state to consequently have a floating potential, whereby the injected charge is held in each pixel 11. That is, a sampling and holding action is performed. Since the discharge channel thus functions as an individual sampling switching element provided in each pixel 11, it is typically expressed by the use of a switching symbol S1. On the other hand, the liquid crystal 9 and the intermediate sheet 3 held between the signal electrodes 101, 102 and the discharge channel function as a sampling capacitor. When the sampling switch S1 is turned on by line sequential scanning, the image signal is held in the sampling capacitor, and each pixel is switched on or off in accordance with the signal voltage level. Even after the sampling switch S1 is turned off, the signal voltage is held in the sampling capacitor, and an active matrixing operation is performed in the display system. An effective voltage applied actually to the liquid crystal 9 is determined by division of the capacitance to the intermediate sheet 3.
In the plasma addressed display system having the structure mentioned above, it is necessary, for raising the resolution thereof, to achieve a higher density of pixels arrayed in rows and columns. Each pixel can be horizontally miniaturized by reducing the line width of each signal electrode, while each pixel can be vertically miniaturized by decreasing the array pitch of the discharge channels. However, since the individual discharge channels are partitioned by barrier ribs, it is technically difficult to significantly reduce the thickness of the barrier ribs, and the minimum thickness is determined to provide a required mechanical strength and so forth. Therefore, if the array pitch of discharge channels is decreased, the thickness of the barrier ribs occupies a greater portion of the display which results in a problem that the area of each opening for actual transmission of light is reduced. In other words, the aperture ratio of the panel is diminished in proportion to an increase of the number of discharge channels, i.e., the number of scans.
A measure for coping with the above problem is disclosed in Japanese Patent Laid-open No. Hei 4 (1992)-265933, which is shown in FIG. 9. As shown in this diagram, column signal electrodes 101, 101', 102, 102', . . . intersect with row discharge channels 51, 52, 53, 54, . . . , and pixels are provided at the intersections. The signal electrodes are so patterned as to be divided into upper and lower portions at the intersections. More specifically, the signal electrodes have a double matrix structure which consists of signal electrodes 101, 102, 103, 104, . . . corresponding to the upper halves of the discharge channels 51-54 and signal electrodes 101', 102', 103', 104', . . . corresponding to the lower halves of the discharge channels 51-54. In this manner, the signal electrodes arrayed orthogonally to the discharge channels 51-54 are multi-matrixed through division into a plurality per scanning unit. More precisely, the signal electrodes are double-matrixed in a form divided into upper and lower parts in a single discharge channel, so that the operation performed therein is equivalent to that in a case where two pixel rows (two scanning lines) are existent in relation to a single discharge channel. Therefore, if the number of scanning lines is fixed, the array pitch of the discharge channels is reduced to a half to consequently facilitate the production process. However, for realizing simultaneous writing in pixels of plural rows relative to a single discharge channel, there are formed some portions where the signal line is rendered extremely thin, as shown in FIG. 9, due to the necessity of separating the signal electrodes. The signal voltage applied to the signal electrode is regulated to a time constant which is determined by the product of the electrode resistance and the pixel capacitance. If the resistance of the signal electrode becomes extremely high, it is impossible to perform satisfactory writing in the entire pixels included in one picture within the time of one frame of the displayed image.
Generally, for execution of a high resolution display by the use of an active matrix type color display system, it is necessary to increase the number of pixels on a screen. In this case, the size of each pixel is reduced, and the time allocated to writing is shortened. In a plasma addressed display system, the pixel size is determined by the array pitch of discharge channels and the width of each signal electrode. Since barrier ribs need to be formed for partitioning the discharge channels in a plasma addressed display system, the aperture ratio of the display panel is extremely lowered, due to the existence of such barrier ribs, in proportion to diminution of the display pitch. One of the means proposed for elimination of the above problem is to write an image signal of plural scanning lines in one discharge channel as described. According to this means, discharge channels are formed at an array pitch corresponding to a plurality of scanning lines subjected to simultaneous writing, and the image signal stored in a line memory is written simultaneously by plasma discharges in one discharge channel. However, this means is also flowed since the signal electrode in each pixel needs to be divided into a plurality of electrodes. As a result, the resistance of the signal electrode is increased. As a result, the waveform of the voltage applied to the signal electrode is rounded off so that the predetermined signal voltage level fails to be applied to the signal electrode.